1. Field of the Invention
The present invention relates to the field of interconnect technology for electrically coupling integrated circuits, and more specifically to high density interconnect platforms.
2. Discussion of Related Art
As integrated circuit (ICs) transistor densities have continued to balloon, the need for input and output bandwidth has also increased. Thus there is now an ever increasing demand on chip interconnect technology to provide high density routing of conductors and to provide increased levels of interconnection in order to prevent the interconnection platform from becoming the bottleneck of systems which utilize modem high speed processors and associated chips.
An exploded view of one example high speed CPU packaging strategy is shown in FIG. 1. A high speed microprocessor 102 having a heat sink 101 attached thereto is connected to a multichip substrate 104 by flip chip solder bumps 106 which enable high density I/O connections between microprocessor 102 and substrate 104. Secondary integrated circuits such as SRAM cache chips, which have large signal interaction with the microprocessor, may also be connected to the multichip substrate 104. The multichip substrate 104 and its associated IC's are then electrically coupled by, for example, solder bumps 108 to a printed wiring board 110 on which the other IC's of the system are connected. The printed wiring board 110 is typically formed from an FR-4 epoxy board, with a single built-up layer 114 on each side connected by plated-through holes (not shown).
Multichip substrate 104 typically comprises an internal BT fiber base board 111 through which plated through holes 113 are fabricated. Formed on the outer surfaces of the BT fiber based board are built up layers 112 of metal and dielectrics for signal routing and bond pad formation.
With the need for increased signal propagation speeds and increased routing densities, material and process development trends have progressed towards achieving greater numbers of layers, thinner dielectrics, smaller via size and finer conductive lines for built up layers 112 and 114. As such, the current approach is to use photodefinable unreinforced polymer dielectrics to provide multi-layer stack-ups and to use microvias instead of plated through holes (PTH) to provide vertical interconnection. In such a process polymers are patterned to define microvias and then thin metal lines are formed directly on the polymers and in the microvias to provide electrical routing.
One problem with this approach is that metals such as copper have significantly lower coefficients of thermal expansion (CTE) than do organic dielectrics such as photo definable polymers. Between periods of microprocessor use and non-use, the CPU package may experience temperature shifts between room temperature (25.degree. C.) and operating temperatures of 100-150.degree. C. Such temperature cycling in the presence of a CTE mismatch creates a tremendous amount of stress within the interconnect platform, which often concentrates around sharp corners of the metal lines. When such stress exists on thin conductive lines or in microvias, adhesion problems often result between the conductive and dielectric layers which can lead to electrical performance degradation and interconnection failure. For example, as shown in FIG. 2a, stress can cause crack 202 propagation across the entire organic polymer dielectric layer 204 causing lift-off of the metal layer 206 above as well as electrical failure of dielectric 204. Additionally, as shown in FIG. 2b, stress caused by bonding and clamping-induced curvature flattening can lead to bond pad 210 lift-off. These and other stress-related problems create an inherent reliability problem in the current art of interconnect technologies.
Thus, what is desired is a method to remove or reduce the stress between rigid dielectrics and metal conductors in a single or multiple layer stack-up so that high density interconnection platforms can be reliably fabricated and operated.